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71M6521DE/DH/FE Data Sheet
1/32768Hz =
30.518μs
IB
IA
VB
VA
13/32768Hz = 397μs
per mux cycle
Figure 4: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer
cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 5: Accumulation Interval
Figure 5 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100
samples of 397μs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50Hz
signal.
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES ( even
though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6ms). Furthermore,
sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation
interval need not be an integer multiple of the signal cycles.
It is important to note that the length of the accumulation interval, as determined by N ACC , the product of
SUM_CYCLES and PRE_SAMPS , is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and
PRE_SAMPS = 00 (42), the resulting accumulation interval is:
τ =
N ACC
f S
=
60 ? 42
32768 Hz
13
=
2520
2520 . 62 Hz
= 999 . 75 ms
This means that accurate time measurements should be based on the RTC, not the accumulation interval.
Page: 16 of 107
Rev 3
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